1. Field of the Invention
The present invention relates to electronic circuitry for integrated circuits. More particularly, the present invention relates to an output buffer circuit which can drive devices from multiple logic families having different voltages representing logic levels.
2. The Prior Art
With recent progress in integrated circuit technology, ICs with logic operating from a Vcc of 3.3 volts have become available. This has caused a shift from the 5 volt Vcc standard used in TTL and CMOS circuits to a Vcc of 3.3 volts which may be used for low voltage TTL and CMOS circuits. The use of both a 5 volt Vcc and a 3.3 volt Vcc in the same overall system circuit design has created difficulties for both system and IC designers. When IC designers design a circuit to interface with other circuits having a Vcc of only either 5 volts or 3.3 volts, problems arise when a circuit designed for a Vcc of 3.3 volts must interface with a circuit designed for a Vcc of 5 volts.
For example, in a hybrid system including both a Vcc of 3.3 volts and a Vcc of 5 volts, the output of a device with a Vcc of 5 volts may be connected to a common node to which is also connected the output of a device having a Vcc of 3.3 volts. A CMOS output buffer of a device with a Vcc of 3.3 volts may typically include a totem pole output for driving the output node. The CMOS totem pole typically includes a P-channel MOS pullup transistor with its source connected to a 3.3 volt Vcc, and an N-Channel MOS pulldown transistor with its source connected to ground, wherein the drains of both the P-channel MOS pullup transistor and the N-Channel MOS pulldown transistor are connected to form the output node of the output buffer. The totem pole output node may typically be connected to a common node in the system.
When a device with a Vcc of 5 volts connected to a common node drives the common node to 5 volts, the P-type drain region of the P-channel MOS pullup transistor in a totem pole also connected to the common node will be pulled above the 3.3 volt Vcc connected to the source of the P-channel MOS pullup transistor in the totem pole. As a result, the junction diode formed by the P-type drain region and the N-well in which the P-channel MOS pullup transistor is formed may become forward biased or the P-channel MOS pullup transistor may be turned on. Either of these occurrences can clamp the common node to the 3.3 volt Vcc of the 3.3 volt device and sink current. If the devices remain in this state, which is quite likely during normal use, a great deal of current will flow from the device with a Vcc of 5 volts to the device with the Vcc of 3.3 volts. This is not only a considerable waste of power, but also has the potential to damage or destroy one or both of the devices.
Several solutions for this problem have been suggested by the prior art. In programmable logic devices (PLD) which typically comprise several configurable function blocks used to implement various logic functions, wherein each configurable function block has a set of I/O buffers which are used to connect the configurable function block to I/O pins, one approach has been to provide a dedicated Vcco pin to the I/O buffers to provide the desired Vcc of either 5 volts or 3.3 volts to each of the I/O buffers in the same configurable logic block. This sets each of the pins (I/O buffers) in the same configurable function block to the desired output voltage.
This approach has several drawbacks. First, the Vcco pins to each of the configurable function blocks use pins which would otherwise be available as additional user I/O pins. Second, it increases the Vcc noise on the chip. Third, it greatly reduces the ability to interconnect the configurable function blocks internally due to constraints on pin locations.
Another approach has been to use specialized integrated circuits designed to interface between logic families. These specialized integrated circuits are known as external translators. They can be either unidirectional or bidirectional. These devices have several drawbacks which may include additional component count, use of valuable board area, higher power consumption (especially for wide busses), a high degree of design complexity, and propagation delay which precludes their use in high performance applications.
Another approach has been to modify the typical CMOS totem pole by floating the N-well in which the P-channel MOS pullup transistor is formed. The N-well is said to float, because rather than have the N-well tied to the Vcc of 3.3 volts, it is indirectly connected to the common node such that when the common node is driven above Vcc, the N-well will follow or float up with the common node, and when the common node is driven below Vcc, the N-well will not float low with the common node. There are several approaches in the prior art to implement a floating N-well.
Dobberpuhl et al., 1992 IEEE International Solid-State Circuits Conference pgs. 106-107, disclose an array of P-Channel transistors used to enable the N-well to float. This approach is not very desirable, however, because it is very vulnerable to latch-up.
Martin, Electronic Design, Apr. 4, 1994, pgs. 67-73 discloses an output scheme using Schottky clamps to implement a floating N-well. The N-well will float because the Schottky diode turn-on voltage is less than the junction diode turn-on voltage of the P-Channel MOS transistor drain region and the turn-on voltage of the P-Channel MOS transistor. This approach is also less than desirable because expensive additional processing is required, and it is also vulnerable to latch-up.
Those of ordinary skill in the art will also realize that while the problem is presently directed to systems having both a device with a Vcc of 5 volts and a device with a Vcc of 3.3 volts, that in the future, further reductions in the operating Vcc of integrated circuits will occur. Accordingly, a general solution to driving devices having different Vcc voltages is required.
It is therefore an object of the present invention to implement an output buffer circuit capable of driving devices from multiple logic families having different Vcc voltage requirements.
Another object of the present invention is to provide a totem pole in an output buffer having a pullup transistor which will not turn on or whose junction diode will not turn on when the output node is driven to a voltage above the Vcc voltage connected to the pullup transistor.
Yet another object of the present invention is to provide an output buffer which does not require a separate pin to program its output voltage level on a pin-by-pin or block-by-block basis.
It is a further object of the present invention to provide an output buffer for a programmable logic device that does not constrain the pin-to-pin connections of the programmable logic device.
It is another object of the present invention to provide a totem pole in an output buffer which is resistant to latch-up.
It is yet another object of the present invention to provide an integrated circuit supplied with a first Vcc having an output buffer with totem pole having a N-channel MOS pullup transistor connected to the first Vcc and an N-channel MOS pulldown transistor connected to ground, and an output node capable of being connected to a common node which may be driven by a device having a second Vcc without sinking current through the N-channel MOS pullup transistor, wherein the second Vcc has a higher voltage than the first Vcc.
It is a further object of the present invention to provide an integrated circuit supplied with a Vcc of 3.3 volts having an output buffer with totem pole having a N-channel MOS pullup transistor connected to a Vcc of 3.3 volts and an N-channel MOS pulldown transistor connected to ground, and an output node capable of being connected to a common node which may be driven to a 5 volts without sinking current through the N-channel MOS pullup transistor.
It is a further object of the present invention to provide a first integrated circuit supplied with a first Vcc having an output buffer a with totem pole having a P-channel MOS pullup transistor disposed in an N-well connected to a second Vcc and an N-channel MOS pulldown transistor, and an output node capable of being connected through a common node to a second integrated circuit supplied with a third Vcc, wherein the third Vcc is higher than the first Vcc, the P-channel MOS pullup transistor does not sink current when the common node is driven to a voltage higher than the first Vcc by the second integrated circuit, and the second Vcc is at least as high as the voltage to which the common node may be driven by the second integrated circuit.
Another object of the present invention is to provide an output totem pole having a P-channel MOS pullup transistor connected to a Vcc of 3.3 volts disposed in an N-well connected to a Vcc of 5 volts and an N-channel MOS pulldown transistor connected to ground, and an output node capable of being connected to a common node which may be driven to 5 volts without sinking current through the P-channel MOS pullup transistor.